Method and system for detecting and performing automatic bank switching for a filter coefficient ram

ABSTRACT

A method for facilitating a dual-bank filter coefficient RAM designed to switch banks automatically during the vertical blanking interval in a television application. The method and system of the present invention allows a micro controller to program a new set of filter coefficients in the memory bank not currently being used, automatically detect when all the coefficients have been written and then automatically switch banks during the vertical blanking interval in the television application.

PRIORITY CLAIM

This application claims the benefit of U.S. Provisional PatentApplication No. 60/392,293, filed Jun. 27, 2002, entitled “METHOD ANDSYSTEM FOR DETECTING AND PERFORMING AUTOMATIC BANK SWITCHING FOR AFILTER COEFFICIENT RAM,” which is incorporated herein by reference.

FIELD OF THE INVENTION

The present invention relates to data transfer and storage in a videoprocessing system.

BACKGROUND OF THE INVENTION

With the advent of digital and high definition television broadcastingmodern television signal processing systems are required to receive anddisplay multiple formats of television broadcasts. Each format hasunique signal qualities and is optimally processed by unique filterconfigurations. It is desirable for the program broadcaster to be ableto switch between formats during the course of the broadcast. It istherefore necessary for the television signal processing system to beable recognize a change in broadcast format and change the filterconfiguration to optimally process the new format.

Changing the filter configuration during a broadcast can result inundesirable disturbances in the picture, such as video flashes, pairingin interlaced signals, loss of picture synchronization, or audiodisturbances. It is advantageous to eliminate these undesirabledisturbances and perform the switch in program formats smoothly so theviewer is unaware of any change.

SUMMARY OF THE INVENTION

In one aspect, the present invention involves a method for managingmemory in a video signal processing device comprising disabling a firstmemory and a second memory, switching an output from the first memory tothe second memory in response to a portion of a video signal, andenabling the first memory and the second memory.

In another aspect, the invention also involves an apparatus forselecting one of a plurality of video filter coefficients comprising afirst memory for storing a first set of video filter coefficients, asecond memory for storing a second set of video filter coefficients, aswitch for selecting either the first memory or the second memory, and abank switching device for detecting a portion of a video signal andchanging the state of the switch.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a multiformat television signal processingsystems,

FIG. 2 is a block diagram of an exemplary implementation of a videoformat converter in a digital video receiving system.

FIG. 3 is a block diagram of an exemplary implementation of memory bankswitching circuitry.

FIG. 4 is a flowchart that illustrates the process of detecting aprogram format change, the process of detecting a vertical blankinginterval and the process of switching the video filter coefficients.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The characteristics and advantages of the present invention will becomemore apparent from the following description, given by way of example.One embodiment of the present invention may be included within anintegrated circuit. Another embodiment of the present invention maycomprises discrete elements forming a circuit.

FIG. 1 is a block diagram of an exemplary digital video receiving system(10) according to the present invention. System (10) includes an antenna(20) and an input processor (22) for together receiving and digitizing abroadcast carrier modulated with signals carrying audio, video, andassociated data. System (10) also includes a demodulator (24) forreceiving and demodulating the digital output from input processor (22).Further, system (10) includes a remote control unit (26) for receivinguser input commands. System (10) also includes one or moredigital-input-to-digital-output or digital-input-to-analog-outputdisplay driver(s) (28) and a respective digital-input or analog-inputdisplay (30) for together converting digital video picture data intovisual representations. In the preferred embodiment, display (30) is amultiformat television display unit and, accordingly, display driver(s)(28) is a suitable multiformat-input-to-digital-output device. While thepresent invention is described in regard to the exemplary embodiment ofFIG. 1 which includes a display device, the invention is also applicableto systems that do not include a display device such as set top boxes,video cassette recorders, and DVD players.

System (10) further includes a video processor (32). In general, videoprocessor (32) receives user input commands from remote control unit(26), receives the demodulated data from demodulator (24), andtransforms the demodulated data into video picture data for displaydriver(s) (28) in accordance with the user input commands. Accordingly,video processor (32) includes a remote interface (34) and a controller(36). Remote interface (34) receives user input commands from remotecontrol unit (26). Controller (36) interprets the input commands andappropriately controls settings for various components of processor (32)to carry out the commands (e.g., channel and/or on-screen display(“OSD”) selections). Video processor (32) further includes a decoder(38) for receiving the demodulated data from demodulator (24) andoutputting a digital signal that is trellis decoded, mapped into bytelength data segments, de-interleaved, and Reed-Solomon error corrected.The corrected output data from decoder (38) is in the form of a MovingPicture Experts Group (“MPEG”) standard compatible transport data streamcontaining program representative multiplexed audio, video, and datacomponents.

Processor (32) further includes a decode packet identifier (“PID”)selector (40) and a transport decoder (42). PID selector (40) identifiesand routes selected packets in the transport stream from decoder (38) totransport decoder (42). Transport decoder (42) digitally demultiplexesthe selected packets into audio data, video data, and other data forfurther processing by processor (32) as discussed in further detailbelow.

The transport stream provided to processor (32) comprises data packetscontaining program channel data, ancillary system timing information,and program specific information such as program content rating andprogram guide information. Using the program specific information,transport decoder (42) identifies and assembles individual data packetsincluding the user selected program channel. Transport decoder (42)directs the ancillary information packets to controller (36) whichparses, collates, and assembles the ancillary information intohierarchically arranged tables.

The system timing information contains a time reference indicator andassociated correction data (e.g., a daylight savings time indicator andoffset information adjusting for time drift, leap years, etc.). Thistiming information is sufficient for an internal decoder (e.g., MPEGdecoder (44), discussed below) to convert the time reference indicatorto a time clock (e.g., United States eastern standard time and date) forestablishing a time of day and date of the future transmission of aprogram by the broadcaster of the program. The time clock is useable forinitiating scheduled program processing functions such as program play,program recording, and program playback.

Meanwhile, the program specific information contains conditional access,network information, and identification and linking data enabling system(10) to tune to a desired channel and assemble data packets to formcomplete programs. The program specific information also containsancillary program content rating information (e.g., an age basedsuitability rating), program guide information (e.g., an ElectronicProgram Guide (“EPG”)) and descriptive text related to the broadcastprograms as well as data supporting the identification and assembly ofthis ancillary information.

System (10) also includes an MPEG decoder (44). Transport decoder (42)provides MPEG compatible video, audio, and sub-picture streams to MPEGdecoder (44). The video and audio streams contain compressed video andaudio data representing the selected channel program content. Thesub-picture data contains information associated with the channelprogram content such as rating information, program descriptioninformation, and the like. MPEG decoder (44) decodes and decompressesthe MPEG compatible packetized audio and video data from transportdecoder (42) and derives decompressed program representative datatherefrom.

MPEG decoder (44) also assembles, collates and interprets thesub-picture data from transport decoder (42) to produce formattedprogram guide data for output to an internal OSD module (not shown). TheOSD module processes the sub-picture data and other information togenerate pixel mapped data representing subtitling, control, andinformation menu displays including selectable menu options and otheritems for presentation on display (30). The control and informationdisplays, including text and graphics produced by the OSD module, aregenerated in the form of overlay pixel map data under direction ofcontroller (36). The overlay pixel map data from the OSD module iscombined and synchronized with pixel representative data from decoder(38) under the direction of controller (36). Combined pixel map datarepresenting a video program on the selected channel together withassociated sub-picture data is encoded by MPEG decoder (44).

System (10) further includes one or more display processor(s) (46). Ingeneral, display processor(s) transform the encoded program andsub-picture data from MPEG decoder (44) into a form compatible withdisplay driver(s) (28). In the exemplary embodiment, displayprocessor(s) (46) include a video format converter (“VFC”) (60) (seeFIG. 2) according to the present invention as discussed further below.

FIG. 2 is a block diagram of an exemplary implementation of a videoformat converter (“VFC”) (60) in a digital video receiving systemaccording to the present invention. The VFC (60) includes a plurality ofparallel video line memories (62), a VFC controller (64), a VFC filter(66), a filter coefficient RAM (70), and a first-in first-out (“FIFO”)data buffer 68. The VFC (60) receives an input video stream (61) fromthe MPEG decoder (44) and transmits an output video stream (69) to thedisplay processors (46). In general, VFC controller 64 controls videoline memories (62) and the VFC filter (66) to store or queue data froman incoming video stream (61). Further, the video filter coefficient RAM(70) is configured to operate in response to the VFC controller (64) tomake the optimal set of video filter coefficients available to the VFCfilter (66) for the display format being processed by the displayprocessor (46).

A change in the display format of the incoming video stream requires achange in the video filter coefficients being used by the VFC filter(66) to produce the best possible picture. However, changing the videofilter coefficients may result in undesirable disturbances in the outputvideo stream, and subsequently the picture, such as video flashes,pairing in interlaced signals, loss of picture synchronization, or audiodisturbances. It is advantageous to eliminate these undesirabledisturbances and perform the switch in program formats smoothly so theviewer is unaware of any change. When the VFC controller (64) determinesthat a change in display format of the incoming video stream hasoccurred, the VFC controller (64) transmits the addresses of the videofilter coefficients for the new display format to the video filtercoefficient RAM (70). After receiving the complete set of addresses forthe video filter coefficients of the new display format from the VFCcontroller (64), the filter coefficient RAM (70) then makes a transitionbetween the video filter coefficient sets of the previous display formatand the new display format during a subsequent vertical blankinginterval.

A television video signal includes video intervals alternating withblanking intervals where the video is interrupted so that display (30)scan beam can be quickly returned to a point where a subsequent scan iscommenced. There are two types of blanking intervals, the horizontalblanking interval which occurs once for each line of the video image andwhich contains a single horizontal sync pulse, and the vertical blankinginterval which occurs after each field of video information. Thevertical blanking interval generally includes six relatively widevertical synchronization pulses preceded by six relatively narrowpre-equalization pulses and followed by six relatively narrowpost-equalization pulses. After the filter coefficient RAM (70) sensesthe vertical synchronization pulses, it initiates the transition betweenthe video filter coefficient sets of the previous display format and thenew display format. Since the transition is made during a verticalblanking interval, when there is no video output, the transition is in amanner to prevent undesirable disturbances in the picture.

FIG. 3 is a block diagram of an exemplary embodiment of the filtercoefficient RAM (70) including an apparatus to control the switching ofmemory banks storing video filter coefficients. The system shown in FIG.3 includes a register bus (370), coefficient address detector (310), abank switching state machine (340), a first input multiplexer (410) andsecond input multiplexer (411), a first RAM (418) and a second RAM (419)and an output multiplexer (422). A portion of the register bus (370)includes an address bus (403,404,408,409). The register bus (370) can beaccessed by the the VFC Controller (64, FIG. 2), the coefficient addressdetector (310), the VFC filter (66, FIG. 2), the first input multiplexer(410) and the second input mutiplexer (411) and is used to read andwrite the banks of filter coefficients that are used by the VFC filter(66, FIG. 2).

The VFC controller (64, FIG. 2) writes the addresses to the RAM (418,419) selected at that time to be in the write mode. This selection ismade via the bank select line (350) from the bank switching statemachine (340). It should be noted that only one input multiplexer(410,411) can be configured to be in the write mode at any one time asthe other input multiplexer (410,411) operates on the inverse of thebank select line (350). Therefore when the bank select line is high, forexample, the first input multiplexer (410) is in the write mode, whilethe second input multiplexer (411) other is in the read mode. When thestate of the bank select line (350) changes state, the function of eachinput multiplexer (410,411) changes in response, thus the first inputmutiplexer (410) is in the read mode while the second input multiplexer(411) is in the write mode. Therefore, only one RAM (418,419) can bewritten to at one time and only one RAM (418,419) can be read from atany one time, dependant on the state of the bank select line (350).

The VFC filter (66, FIG. 2) requests the address of the video filtercoefficients currently required from the RAM (418,419) via the readaddress line (403,408) of the input multiplexer (410,411) currently inthe read mode. The requested address information is then read via thebank data line (424) connected to the VFC filter (66, FIG. 2).

The address detector (310) monitors the data on the register bus (370)to determine the status of writing addresses to the RAMs by the VFCcontroller (64, FIG. 2). When the address detector (310) detectsaddresses of filter coefficients being written a RAM (418,419), whichindicates a change in the format of the incoming video stream (61, FIG.2), the address detector (310) determines when the last address of thefilter coefficient has been written, either by counting the number ofaddresses written and comparing that number against a known quantity orby an alternate method, and then sets the last_addr_written flag to thebank switching circuitry (340). The last_addr_written flag is set bychanging the state of the last flag written line (320) connecting thecoefficient address detector (310) and the bank switching circuitry(340). After observing the “last_addr_written” flag, the bank switchingcircuitry (340) monitors the vertical blanking line (330) for the nextvertical blanking interval, which is indicated by a vertical sync pulseassociated with the input video stream as described previously.

After the vertical blanking interval is indicated, the bank switchingcircuitry, (340) disables the RAMS (418,419) via the chip enable/disableline (350) to prevent false reads or writes from occurring. A false reador write may occur when information is being read from the RAM (418,419)and written to the RAM (418, 419) at the same time. In this instance,the VFC filter (66, FIG. 2) may erroneously read video filtercoefficients from both the new set of video filter coefficients beingwritten and the set being written over, thereby resulting in anincorrect set of video filter coefficients. Additionally, similar errorsmay also occur with a single address being read and written at the sametime. After the RAMS (418,419) are disabled, the bank switchingcircuitry (340) switches the RAM (418,419) to be read via the bankselect line (350) as described previously. The bank select line (350)concurrently is used to switch the state of the input multiplexers.(410,411) Switching the state of the input multiplexers. (410,411)connects the read clock (401) and read address (403) lines to the RAM(418,419) previously set to write and connects the write clock and writeaddress lines (416) the RAM (418,419) previously set to read. The inputmultiplexers are connected to the RAMS (418,419) via conductive lines.(414, 416) After the bank switching circuitry (340) changes the state ofthe bank select line (350) it enables the RAMS (418,419) via the chipenable/disable line. (350) At this time, the video filter coefficientsfor the new video format are able to be read by the VFC filter (66, FIG.2) via the bank data line (424) and the output multiplexer (422).

FIG. 4 is a flowchart illustrating the process of detecting a programformat change, the process of detecting a vertical blanking interval andthe process of switching the video filter coefficients according to thefollowing exemplary memory management technique of the presentinvention:

-   1. The coefficient address detector (310) monitors the register bus    to determine if new addresses are being written by the VFC    controller (64) to the RAMs (418,419).-   2. After the coefficient address detector (310) determines new    addresses are being written, indicating a change in the input video    format, the coefficient address detector (310) monitors the    addresses being written to determine when the last address has been    written.-   3. After the last address has been written by the VFC controller,    the coefficient address detector (310) sets the last_addr_written    flag (320).-   4. When the bank switching state machine (340) observes the    last_addr_written flag, it monitors the vertical blanking line (330)    to determine the start of the next vertical blanking period.-   5. After the next vertical blanking period is indicated via the    vertical blanking line (330), the bank switching state machine (340)    disables the RAMs (418,419) via the enable disable line (350).-   6. The bank switching state machine (340) then switches the    read/write functions of the RAMs (418,419) via the bank select line    (350).-   7. The bank switching state machine (340) then enables the RAMs    (418,419) via the via the enable disable line (350).-   8. The address detector then returns to the initial state of    monitoring the register bus to determine if new addresses are being    written by the VFC controller (64) to the RAMs (418,419).

While the present invention has been described with reference to thepreferred embodiments, it is apparent that various changes may be madein the embodiments without departing from the spirit and the scope ofthe invention, as defined by the appended claims.

1. A method for managing memory in a video signal processing devicecomprising: disabling a first memory and a second memory; switching anoutput from said first memory to said second memory in response to aportion of a video signal; and enabling said first memory and saidsecond memory.
 2. The method for managing memory of claim 1 wherein saidportion of a video signal is a video blanking interval.
 3. The methodfor managing memory of claim 2, wherein said video blanking interval isa vertical video blanking interval.
 4. The method for managing memory ofclaim 1 wherein said output is connected to a video filter.
 5. Themethod for managing memory of claim 4 wherein said first memory and saidsecond memory store video filter coefficient data.
 6. The method formanaging memory of claim 5 wherein said video filter coefficient data isthe memory address data of video filter coefficients.
 7. The method formanaging memory of claim 1 wherein disabling said first memory and saidsecond memory comprises the steps of disabling the read and writefunctions of said first memory and said second memory.
 8. A method forchanging video filter coefficients in a video signal processing devicecomprising: detecting a change in a video display format of a videosignal; writing at least one address of a bank of video filtercoefficients to a first memory; disabling said first memory; switchingan output of a second memory to said first memory in response to aportion of a video signal; and enabling said first memory.
 9. The methodfor changing video filter coefficients in a video signal processingdevice of claim 8 wherein said portion of a video signal is a videoblanking interval.
 10. The method for changing video filter coefficientsin a video signal processing device of claim 9, wherein said videoblanking interval is a vertical video blanking interval.
 11. The methodfor changing video filter coefficients in a video signal processingdevice of claim 1 wherein said output is connected to a video filter.12. The method for changing video filter coefficients in a video signalprocessing device of claim 4 wherein said first memory and said secondmemory store video filter coefficient data.
 13. An apparatus forselecting one of a plurality of video filter coefficients comprising: afirst memory for storing a first set of video filter data; a secondmemory for storing a second set of video filter data; a switch (422) forselecting either said first memory or said second memory; and a bankswitching device for detecting a portion of a video signal and changingthe state of said switch.
 14. The apparatus of claim 13 wherein saidportion of a video signal is a video blanking interval.
 15. Theapparatus of claim 14, wherein said video blanking interval is avertical video blanking interval.
 16. The apparatus of claim 13 whereinsaid first set of video filter data and said second set of video filterdata are a plurality of memory address locations of video filtercoefficients.
 17. The apparatus of claim 13 wherein said first set ofvideo filter data and said second set of video filter data are aplurality of video filter coefficients.
 18. The apparatus of claim 13wherein said switch is a multiplexer.
 19. The apparatus of claim 13wherein said apparatus is included within an integrated circuit.